大型地址空间机中转换表管理的体系结构支持

Jerome C. Huck, Jim Hays
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引用次数: 144

摘要

虚拟内存页转换表提供了从虚拟地址到物理地址的映射。当硬件控制的翻译暂存缓冲区(tlb)不包含翻译时,这些表提供翻译。这些表的结构和管理方法各不相同,从完全的硬件实现到完整的基于软件的算法。进程使用的虚拟地址空间的大小正在迅速增长,超过32位地址。随着已利用地址空间的增加,新的问题和问题浮出水面。管理页转换表的传统方法不适合大型地址空间体系结构。这里描述的哈希页表(HPT)提供了一个非常快速和空间高效的转换表,通过在硬件和软件之间划分TLB管理职责来减少开销。测量结果表明,它适用于各种操作系统和工作负载,特别是大型虚拟地址空间机。在超过40亿条指令的模拟中,可以观察到5%到10%的改进。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Architectural Support For Translation Table Management In Large Address Space Machines
Virtual memory page translation tables provide mappings from virtual to physical addresses. When the hardware controlled Translation Lookaside Buffers (TLBs) do not contain a translation, these tables provide the translation. Approaches to the structure and management of these tables vary from full hardware implementations to complete software based algorithms. The size of the virtual address space used by processes is rapidly growing beyond 32 bits of address. As the utilized address space increases, new problems and issues surface. Traditional methods for managing the page translation tables are inappropriate for large address space architectures. The Hashed Page Table (HPT), described here, provides a very fast and space efficient translation table that reduces overhead by splitting TLB management responsibilities between hardware and software. Measurements demonstrate its applicability to a diverse range of operating systems and workloads and, in particular, to large virtual address space machines. In simulations of over 4 billion instructions, improvement of 5 to 10% were observed.
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