Comparative study between HDLs simulation and Matlab for image processing

Digital Image Processing (DIP) plays a vital role in the analysis and interpretation of remotely sensed data. It forms core research area within engineering and computer science disciplines too. This paper describes a proposal design for image processing in Verilog and that can be applied for any format of images like jpg, gif, bmp etc. The main advantage of using Verilog to simulate DIP of any logical inputs is related with the possibility of an immediate FPGA based hardware implementation. Our algorithm is designed in Verilog and simulated using the Matlab and Modelsim. In fact, the input image is converted to text/pixel using Matlab and results are stored in a new text file. Using Verilog with test bench program, the inputs, outputs and memory locations are assigned in the form of text file. Then, the output texts file back to image after a conversion step using Matlab. A comparative study between HDLs Simulation and Matlab are conducted. Obtained results show well the efficiency of the proposed design. As an extension of this work, we aim to implement an efficient FPGA based hardware design for a set of image processing, enhancement, and filtering algorithms.