采用螺旋堆叠电感的全集成5-6 GHz CMOS可变增益LNA

Chieh-Min Lo, Shih-Fong Chao, Chiajung Chang, Huei Wang
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引用次数: 6

摘要

本文介绍了一种适用于IEEE 802.11a无线局域网的5-6 GHz CMOS可变增益低噪声放大器(VGLNA)的设计与实现,该放大器采用台积电0.18 μ m 1P6M标准CMOS工艺制作。在本设计中,采用螺旋堆叠电感和电流转向技术分别实现了芯片尺寸的小型化和增益控制范围的宽化。该VGLNA在高增益模式下的噪声系数为3.1 dB,小信号增益为19 dB, IIP3为-9 dBm。切换到低增益模式时,测量到增益为-19 dB, IIP3为-4 dBm。芯片尺寸仅为0.56 mm2
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Fully Integrated 5-6 GHz CMOS Variable-Gain LNA Using Helix-stacked Inductors
This paper presents the design and implementation of a 5-6 GHz CMOS variable-gain low noise amplifier (VGLNA) for IEEE 802.11a WLAN application, fabricated on TSMC 0.18-mum 1P6M standard CMOS process. In this design, miniature chip size and wide gain-control range are achieved by using helix-stacked inductors and current steering technology, respectively. This VGLNA exhibits a noise figure of 3.1 dB, small signal gain of 19 dB, and IIP3 of -9 dBm while in its high gain mode. A gain of -19 dB with IIP3 of -4 dBm were measured while switching into its low gain mode. The chip size is only 0.56 mm2
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