深亚微米集成电路中划痕引起的开放缺陷及成品率模型

IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 1900-01-01 DOI:10.1109/DDECS.2007.4295314

Wlodzimierz Jonca

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Open Defects Caused by Scratches and Yield Modelling in Deep Sub-micron Integrated Circuit

This paper tries to find out whether commonly used spot defect fault model is still viable for deep sub-micron (DSM) integrated circuits' test and yield model. It is believed that for DSM products spot defects may be no longer major source of yield loss. Results from number of computer experiments are presented and discussed.

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IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems

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