Modeling the Effects of SBD, HCI, and NBTI in CMOS Voltage Controlled Oscillator Design for PLL Applications

In this paper, two different structures of phase locked loop (PLL) are examined and designed in 0.13 µm n-well CMOS process technology. The two PLLs only differ in voltage-controlled oscillator (VCO): current starved and LC VCOs. Using device degradation models and equations, their performances are investigated under the combined effects of soft breakdown, hot carrier injections, and negative bias temperature instability. It is observed in the current starved VCO that the gain reduces by 33.5%, the maximum frequency decreases from 1180 MHz to 1100 MHz, and the phase noise increases from −107.6 dBc/Hz to −103.5 dBc/Hz at 1 MHz offset frequency after 6 hours of stress. The varactor degradation in LC voltage-controlled oscillator causes a decrease in the mean capacitance, resulting in increased oscillation frequency. In addition, the phase noise increases from −120 dBc/Hz to −117.2 dBc/Hz at 1 MHz frequency.