基于功率级差的噪声消除硬件/软件协同设计

2015 International Conference on Advanced Technologies for Communications (ATC) Pub Date : 2015-10-01 DOI:10.1109/ATC.2015.7388404

Van Phu Ha, Duc Minh Nguyen, Quang Hieu Dang

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引用次数: 1

摘要

本文采用硬件/软件协同设计的方法，在Xilinx FPGA SoC中实现了基于功率级差(PLD)的噪声消除算法。通过软硬件协同设计，该算法的复杂控制部分可以在软件中快速部署，而计算部分则可以在硬件中有效实现。因此，该系统不仅可以处理实时输入数据，而且消耗的硬件资源很少。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Hardware/software co-design of power level difference based noise cancellation

In this paper, the Power Level Difference (PLD)-based noise cancelling algorithm is implemented in a Xilinx FPGA SoC using hardware/software co-design methodology. Thanks to the hardware/software co-design, the complex control part of the algorithm can be fast deployed in software meanwhile the computational part is effectively implemented in hardware. Therefore, the system can not only process the real-time input data but also consumes few hardware resource.

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来源期刊

2015 International Conference on Advanced Technologies for Communications (ATC)

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