Heetae Kim, Inhyuk Choi, Jaeil Lim, Hyunggoy Oh, Sungho Kang
{"title":"过程变化感知桥接故障分析","authors":"Heetae Kim, Inhyuk Choi, Jaeil Lim, Hyunggoy Oh, Sungho Kang","doi":"10.1109/ISOCC.2016.7799830","DOIUrl":null,"url":null,"abstract":"Bridge faults are important that cause a reliability concern. Since process variation affects the bridge faults, it should be considered for bridge fault analysis. This paper proposes a new analysis method for resistive bridge faults considering process variation. The proposed method analyzes defect coverage for resistive bridge faults by using circuit level modeling. The proposed method uses the lower level analysis and it reduces redundant test patterns for bridge test.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Process variation-aware bridge fault analysis\",\"authors\":\"Heetae Kim, Inhyuk Choi, Jaeil Lim, Hyunggoy Oh, Sungho Kang\",\"doi\":\"10.1109/ISOCC.2016.7799830\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Bridge faults are important that cause a reliability concern. Since process variation affects the bridge faults, it should be considered for bridge fault analysis. This paper proposes a new analysis method for resistive bridge faults considering process variation. The proposed method analyzes defect coverage for resistive bridge faults by using circuit level modeling. The proposed method uses the lower level analysis and it reduces redundant test patterns for bridge test.\",\"PeriodicalId\":278207,\"journal\":{\"name\":\"2016 International SoC Design Conference (ISOCC)\",\"volume\":\"32 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 International SoC Design Conference (ISOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISOCC.2016.7799830\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC.2016.7799830","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Bridge faults are important that cause a reliability concern. Since process variation affects the bridge faults, it should be considered for bridge fault analysis. This paper proposes a new analysis method for resistive bridge faults considering process variation. The proposed method analyzes defect coverage for resistive bridge faults by using circuit level modeling. The proposed method uses the lower level analysis and it reduces redundant test patterns for bridge test.