P. Chen, E. Cartier, R. Carter, T. Kauerauf, C. Zhao, J. Pétry, V. Cosnier, Z. Xu, A. Kerber, W. Tsai, E. Young, S. Kubicek, M. Caymax, W. Vandervorst, S. De Gendt, M. Heyns, M. Copel, W. Besling, P. Bajolet, J. Maes
{"title":"锆铝酸盐基高钾栅极堆的热稳定性和可扩展性","authors":"P. Chen, E. Cartier, R. Carter, T. Kauerauf, C. Zhao, J. Pétry, V. Cosnier, Z. Xu, A. Kerber, W. Tsai, E. Young, S. Kubicek, M. Caymax, W. Vandervorst, S. De Gendt, M. Heyns, M. Copel, W. Besling, P. Bajolet, J. Maes","doi":"10.1109/VLSIT.2002.1015448","DOIUrl":null,"url":null,"abstract":"It is demonstrated that a narrow composition range exists in the ZrAl/sub x/O/sub y/ mixed oxide system between 25 and 50 mol% Al/sub 2/O/sub 3/, where the crystallization temperature exceeds 950/spl deg/C and at the same time the k-values remain larger than 12. In this composition range, enhanced thermal stability for better integration of the ZrAl/sub x/O/sub y/ gate dielectric in a conventional poly-Si device process is observed. It is also shown that thin interfacial oxides strongly enhance the electrical stability while allowing for thickness scaling down to /spl sim/1 nm, providing gate leakage current reductions of two to three orders of magnitude.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Thermal stability and scalability of Zr-aluminate-based high-k gate stacks\",\"authors\":\"P. Chen, E. Cartier, R. Carter, T. Kauerauf, C. Zhao, J. Pétry, V. Cosnier, Z. Xu, A. Kerber, W. Tsai, E. Young, S. Kubicek, M. Caymax, W. Vandervorst, S. De Gendt, M. Heyns, M. Copel, W. Besling, P. Bajolet, J. Maes\",\"doi\":\"10.1109/VLSIT.2002.1015448\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"It is demonstrated that a narrow composition range exists in the ZrAl/sub x/O/sub y/ mixed oxide system between 25 and 50 mol% Al/sub 2/O/sub 3/, where the crystallization temperature exceeds 950/spl deg/C and at the same time the k-values remain larger than 12. In this composition range, enhanced thermal stability for better integration of the ZrAl/sub x/O/sub y/ gate dielectric in a conventional poly-Si device process is observed. It is also shown that thin interfacial oxides strongly enhance the electrical stability while allowing for thickness scaling down to /spl sim/1 nm, providing gate leakage current reductions of two to three orders of magnitude.\",\"PeriodicalId\":103040,\"journal\":{\"name\":\"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)\",\"volume\":\"108 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-06-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2002.1015448\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2002.1015448","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Thermal stability and scalability of Zr-aluminate-based high-k gate stacks
It is demonstrated that a narrow composition range exists in the ZrAl/sub x/O/sub y/ mixed oxide system between 25 and 50 mol% Al/sub 2/O/sub 3/, where the crystallization temperature exceeds 950/spl deg/C and at the same time the k-values remain larger than 12. In this composition range, enhanced thermal stability for better integration of the ZrAl/sub x/O/sub y/ gate dielectric in a conventional poly-Si device process is observed. It is also shown that thin interfacial oxides strongly enhance the electrical stability while allowing for thickness scaling down to /spl sim/1 nm, providing gate leakage current reductions of two to three orders of magnitude.
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