{"title":"系统的VHDL代码生成利用流水线操作生成的高级综合","authors":"P. Arató, T. Kandár","doi":"10.1109/ISP.2003.1275837","DOIUrl":null,"url":null,"abstract":"We present a method for systematic VHDL code generation from a data-flow representation. In such cases, a methodology is needed that yields a hardware description, which are synthetized and mapped into an FPGA. This procedure speeds up the development of the prototype, reduces the time-to-market, and helps the logic and timing simulation.","PeriodicalId":285893,"journal":{"name":"IEEE International Symposium on Intelligent Signal Processing, 2003","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Systematic VHDL code generation using pipeline operations produced by high level synthesis\",\"authors\":\"P. Arató, T. Kandár\",\"doi\":\"10.1109/ISP.2003.1275837\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a method for systematic VHDL code generation from a data-flow representation. In such cases, a methodology is needed that yields a hardware description, which are synthetized and mapped into an FPGA. This procedure speeds up the development of the prototype, reduces the time-to-market, and helps the logic and timing simulation.\",\"PeriodicalId\":285893,\"journal\":{\"name\":\"IEEE International Symposium on Intelligent Signal Processing, 2003\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-09-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE International Symposium on Intelligent Signal Processing, 2003\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISP.2003.1275837\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Symposium on Intelligent Signal Processing, 2003","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISP.2003.1275837","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Systematic VHDL code generation using pipeline operations produced by high level synthesis
We present a method for systematic VHDL code generation from a data-flow representation. In such cases, a methodology is needed that yields a hardware description, which are synthetized and mapped into an FPGA. This procedure speeds up the development of the prototype, reduces the time-to-market, and helps the logic and timing simulation.
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