顺序电路中功率降低的脱敏

Xiangfeng Chen, P. Pan, C. Liu
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引用次数: 3

摘要

我们描述了一种在顺序电路中降低功率的技术。电路中的现有信号用于选择性地禁用某些寄存器,以便电路的一部分将被停用。因此,电路的平均功耗降低的代价是面积和延迟的小幅增加。我们提出了一种算法来确定每个寄存器的脱敏信号。根据我们的实验结果,在许多基准电路中实现了大量的功耗降低。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Desensitization for power reduction in sequential circuits
We describe a technique for power reduction in sequential circuits. Existing signals in the circuit are used to selectively disable some of the registers so that a portion of the circuit will be deactivated. Consequently, average power consumption in the circuit is reduced at a cost of small increases in area and delay. We present an algorithm for determining the desensitizing signal for each register. A significant amount of power reduction is achieved in a number of benchmark circuits according to our experimental results.
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