Systolic cellular logic: architecture and performance evaluation

We describe a systolic cellular logic architecture implemented in the systolic cellular logic (SCL) VLSI chip. The SCL chip's hardware support for virtual processing is intended to provide low cost, high performance image processing. We present empirical performance data for the Abingdon Cross benchmark which indicate that the SCL chip successfully delivers high performance at a relatively low cost. We further substantiate the SCL's success with empirical performance data for a complete experimental shape extraction protocol based on mathematical morphology.