T. Mizuno, T. Irisawa, N. Hirashita, Y. Moriyama, T. Numata, T. Tezuka, N. Sugiyama, S. Takagi
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Novel Anisotropic Strain Engineering on (110)-Surface SOI CMOS Devices using Combination of Local/Global Strain Techniques
We have experimentally studied a new (HO)-surface anisotropic strained-SOI, using the combination of partially-strained global SGOI substrates and the uniaxial relaxation effects in the narrow SiGe layers. We have demonstrated much larger drain current Id enhancement of (110) anisotropic strained-SOIs against (HO)-SOIs than that of biaxial-strained ones. The optimum (110) strained-SOI CMOS consists of the biaxial strained n-MOS and the anisotropic strained p-MOS for the larger drain currents and the simple fabrication processes
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