Low Delay Based 4 Bit QSD Adder/Subtraction Number System by Reversible Logic Gate

In the Modern computers for performing the operationof ALU (Arithmetic Logic Unit) like Addition, Subtraction, different types of adders are using for achieving low delay and fastoutput. QSD numbers are using for giving the carry-free additionso that ALU operations can perform in low delay and speed of themodern computer can increase. In the modern digital system fastadder, Subtraction can perform by use QSD numbers. The rangeof QSD numbers is -3 to +3. In this paper, we are performing the 4Bit QSD Addition and subtraction by Reversible Logic Gate basedFull adder. For performing fast operation, we are also introducingPipelining so that delay can be further reduced in the process ofaddition and subtraction. As we can see from the results session, the delay get reduce up to 92 % by apply Reversible Logic Gatebased full adder with Pipelining.