{"title":"一种新型功率门控数字控制振荡器","authors":"Amr Lotfy, M. Ghoneima, M. Abdel-Moneum","doi":"10.1109/ICEAC.2011.6136677","DOIUrl":null,"url":null,"abstract":"In this paper a novel power gated digitally controlled oscillator (DCO) is presented. The DCO is suitable for integration in various systems such as clock generation circuits, clock and data recovery, and clocking schemes for high speed links. Simulations of the proposed DCO on 65nm TSMC technology show frequency range of 2.5 GHz to 6.8 GHz across all corners. The proposed DCO consumes only 1.7 mW at 3 GHz and 3.2 mW at 6.8 GHz with estimated layout area of 70∗70 μm2. The phase noise of the free running DCO is −92 dBc/Hz measured at 1 MHz offset from a 3.4 GHz center frequency.","PeriodicalId":199442,"journal":{"name":"2011 International Conference on Energy Aware Computing","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A novel power gated digitally controlled oscillator\",\"authors\":\"Amr Lotfy, M. Ghoneima, M. Abdel-Moneum\",\"doi\":\"10.1109/ICEAC.2011.6136677\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper a novel power gated digitally controlled oscillator (DCO) is presented. The DCO is suitable for integration in various systems such as clock generation circuits, clock and data recovery, and clocking schemes for high speed links. Simulations of the proposed DCO on 65nm TSMC technology show frequency range of 2.5 GHz to 6.8 GHz across all corners. The proposed DCO consumes only 1.7 mW at 3 GHz and 3.2 mW at 6.8 GHz with estimated layout area of 70∗70 μm2. The phase noise of the free running DCO is −92 dBc/Hz measured at 1 MHz offset from a 3.4 GHz center frequency.\",\"PeriodicalId\":199442,\"journal\":{\"name\":\"2011 International Conference on Energy Aware Computing\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 International Conference on Energy Aware Computing\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICEAC.2011.6136677\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 International Conference on Energy Aware Computing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEAC.2011.6136677","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A novel power gated digitally controlled oscillator
In this paper a novel power gated digitally controlled oscillator (DCO) is presented. The DCO is suitable for integration in various systems such as clock generation circuits, clock and data recovery, and clocking schemes for high speed links. Simulations of the proposed DCO on 65nm TSMC technology show frequency range of 2.5 GHz to 6.8 GHz across all corners. The proposed DCO consumes only 1.7 mW at 3 GHz and 3.2 mW at 6.8 GHz with estimated layout area of 70∗70 μm2. The phase noise of the free running DCO is −92 dBc/Hz measured at 1 MHz offset from a 3.4 GHz center frequency.
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