{"title":"采用0.18 μm CMOS技术的19.1 dbm全集成24ghz功率放大器","authors":"Jing-Lin Kuo, Zuo‐Min Tsai, Huei Wang","doi":"10.1109/emicc.2008.4772353","DOIUrl":null,"url":null,"abstract":"A 24 GHz, 19.1 dBm fully-integrated power amplifiers (PA) was designed and fabricated in the 0.18-mum deep n-well (DNW) CMOS technology. This power amplifier is a 2-stage design using cascode RF NMOS configuration and has a maximum measured output power of 19.1 dBm, an OP1dB of 13.3 dBm, a power added efficiency (PAE) of 15.6%, and a linear gain of 18.8 dB when VDD and DNW are both biased at 3.6 V. The chip size is only 0.56 times 0.58 mm2. To the authorpsilas knowledge, this PA demonstrates the highest output power of +19.1 dBm among the reported PAs above 15 GHz in CMOS processes.","PeriodicalId":371257,"journal":{"name":"2008 European Conference on Wireless Technology","volume":"56 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A 19.1-dBm fully-integrated 24 GHz power amplifier using 0.18-μm CMOS technology\",\"authors\":\"Jing-Lin Kuo, Zuo‐Min Tsai, Huei Wang\",\"doi\":\"10.1109/emicc.2008.4772353\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 24 GHz, 19.1 dBm fully-integrated power amplifiers (PA) was designed and fabricated in the 0.18-mum deep n-well (DNW) CMOS technology. This power amplifier is a 2-stage design using cascode RF NMOS configuration and has a maximum measured output power of 19.1 dBm, an OP1dB of 13.3 dBm, a power added efficiency (PAE) of 15.6%, and a linear gain of 18.8 dB when VDD and DNW are both biased at 3.6 V. The chip size is only 0.56 times 0.58 mm2. To the authorpsilas knowledge, this PA demonstrates the highest output power of +19.1 dBm among the reported PAs above 15 GHz in CMOS processes.\",\"PeriodicalId\":371257,\"journal\":{\"name\":\"2008 European Conference on Wireless Technology\",\"volume\":\"56 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 European Conference on Wireless Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/emicc.2008.4772353\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 European Conference on Wireless Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/emicc.2008.4772353","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 19.1-dBm fully-integrated 24 GHz power amplifier using 0.18-μm CMOS technology
A 24 GHz, 19.1 dBm fully-integrated power amplifiers (PA) was designed and fabricated in the 0.18-mum deep n-well (DNW) CMOS technology. This power amplifier is a 2-stage design using cascode RF NMOS configuration and has a maximum measured output power of 19.1 dBm, an OP1dB of 13.3 dBm, a power added efficiency (PAE) of 15.6%, and a linear gain of 18.8 dB when VDD and DNW are both biased at 3.6 V. The chip size is only 0.56 times 0.58 mm2. To the authorpsilas knowledge, this PA demonstrates the highest output power of +19.1 dBm among the reported PAs above 15 GHz in CMOS processes.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
