J. Bouloc, L. Nony, C. Loppacher, W. Rahajandraibe, F. Bocquet, Lakhdar Zaïd
{"title":"基于fpga的可编程数字锁相环,具有很高的频率分辨率","authors":"J. Bouloc, L. Nony, C. Loppacher, W. Rahajandraibe, F. Bocquet, Lakhdar Zaïd","doi":"10.1109/ICECS.2011.6122290","DOIUrl":null,"url":null,"abstract":"A FPGA-based tunable all-digital control system featuring high resolution all-digital PLL is presented. The whole system has been designed under Simulink environment and synthesized with QuartusII. The system can achieve very high frequency resolution (0.1Hz) within a frequency range of 20kHz to 60MHz.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"FPGA-based programmable digital PLL with very high frequency resolution\",\"authors\":\"J. Bouloc, L. Nony, C. Loppacher, W. Rahajandraibe, F. Bocquet, Lakhdar Zaïd\",\"doi\":\"10.1109/ICECS.2011.6122290\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A FPGA-based tunable all-digital control system featuring high resolution all-digital PLL is presented. The whole system has been designed under Simulink environment and synthesized with QuartusII. The system can achieve very high frequency resolution (0.1Hz) within a frequency range of 20kHz to 60MHz.\",\"PeriodicalId\":251525,\"journal\":{\"name\":\"2011 18th IEEE International Conference on Electronics, Circuits, and Systems\",\"volume\":\"9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 18th IEEE International Conference on Electronics, Circuits, and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2011.6122290\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2011.6122290","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
FPGA-based programmable digital PLL with very high frequency resolution
A FPGA-based tunable all-digital control system featuring high resolution all-digital PLL is presented. The whole system has been designed under Simulink environment and synthesized with QuartusII. The system can achieve very high frequency resolution (0.1Hz) within a frequency range of 20kHz to 60MHz.