Soft-decision LCC Decoder Architecture with n=4 for RS(255,239)

In this work we present a novel architecture for a soft-decision Reed-Solomon LCC decoder. In our decoder the data sorted and stored in the Multiplicity Assignment stage are different from other authors’ work. We present architectures for the Syndrome Update and Symbol Modification blocks that are adapted to the proposed sorting stage. We present implementation results for ASIC and FPGA that show that this architecture can reach high performance and low latency when compared with similar decoders. For example, in ASIC, our decoder requires 40% less area than a specific state-of-the-art decoder, while still has 40% higher throughput and 0.07 dB coding gain over that decoder.