Electrical package modeling for high power RF semiconductor devices

A modeling procedure is developed for generating electrical package models for air-cavity metalized ceramic packages. Such models are capable of accounting for parasitic effects associated with the capacitance of the bonding pads in the package and the inductance of the bond wires. We have applied this modeling procedure to extract package equivalent circuit models for some of Motorola's LDMOS RF power transistors. The models have been validated up to the third harmonic with respect to the device's operating frequency. It has been demonstrated that the package parasitic effects contribute significantly to an accurate prediction of the packaged transistor nonlinear performance.