{"title":"使用抽象指令级工作负载模型评估平台架构性能","authors":"J. Kreku, Tarja Kauppi, J. Soininen","doi":"10.1109/ISSOC.2004.1411143","DOIUrl":null,"url":null,"abstract":"Evaluation of platform performance is critical in the optimisation and validation of integrated application domain-specific multiprocessor systems. This work describes a method for creating abstract instruction-level workload models from source code, and a method for modelling multi-processor platforms. The approaches are validated by simulating complex use cases in a multiprocessor platform and comparing some of the results to measurements obtained from a prototype product. The approach is targeted at defining architecture parameters and to feature feasibility studies at product concept creation phase.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"83 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"Evaluation of platform architecture performance using abstract instruction-level workload models\",\"authors\":\"J. Kreku, Tarja Kauppi, J. Soininen\",\"doi\":\"10.1109/ISSOC.2004.1411143\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Evaluation of platform performance is critical in the optimisation and validation of integrated application domain-specific multiprocessor systems. This work describes a method for creating abstract instruction-level workload models from source code, and a method for modelling multi-processor platforms. The approaches are validated by simulating complex use cases in a multiprocessor platform and comparing some of the results to measurements obtained from a prototype product. The approach is targeted at defining architecture parameters and to feature feasibility studies at product concept creation phase.\",\"PeriodicalId\":268122,\"journal\":{\"name\":\"2004 International Symposium on System-on-Chip, 2004. Proceedings.\",\"volume\":\"83 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-11-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 International Symposium on System-on-Chip, 2004. Proceedings.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSOC.2004.1411143\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSOC.2004.1411143","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Evaluation of platform architecture performance using abstract instruction-level workload models
Evaluation of platform performance is critical in the optimisation and validation of integrated application domain-specific multiprocessor systems. This work describes a method for creating abstract instruction-level workload models from source code, and a method for modelling multi-processor platforms. The approaches are validated by simulating complex use cases in a multiprocessor platform and comparing some of the results to measurements obtained from a prototype product. The approach is targeted at defining architecture parameters and to feature feasibility studies at product concept creation phase.
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