一种动态可重构协处理器的设计,用于媒体处理和工业控制应用中的灵活精确矩阵算法

Hao Liu, Zhaolin Li, Zhixiang Chen
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引用次数: 1

摘要

深微米半导体技术使我们能够在单个中等尺寸的芯片中集成更多的算术和逻辑单元,因此许多媒体处理和工业控制应用可以利用高性能,低功耗但不昂贵的处理器来满足更密集的计算或定时需求。动态可重构结构带来了一种新的设计范式,在性能和灵活性之间取得了良好的平衡,可以实现像硬线一样的性能,也可以通过更新软件来定制设计。我们提出了一种动态可重构协处理器,用于灵活的精确矩阵算法。它采用几个动态可重构的多运算运算单元,针对高性能媒体处理和工业控制应用。分析并实现了四种典型的协处理器应用,并与ARM920EJ-S和TI TMS320C6713 DSP处理器的实现进行了性能对比。实验结果表明,采用高并行算法的协处理器具有较高的加速系数。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design of a dynamic reconfigurable coprocessor for flexible precision matrix algorithms in media processing and industrial control applications
Deep-micron semiconductor technology enables us to integrate more arithmetic and logic units in single modestly sized chip, so that many media processing and industrial control applications can utilize high performance, low power but not costly processors to meet more intensive computing or timing demands. Dynamic reconfigurable structure brings out a new design paradigm with a good balance between performance and flexibility, which can achieve hard-wired like performance and can be custom designed just by updating software. We propose a dynamic reconfigurable coprocessor for flexible precision matrix algorithms. It employs several dynamic reconfigurable multi-operation arithmetic units, aims at high-performance media processing and in industrial control applications. We analyze and implement four typical applications on the coprocessor, and contrast performances with implementations of ARM920EJ-S and TI TMS320C6713 DSP processor. Experimental result shows that the coprocessor has high speed-up factors with high-parallel algorithms.
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