{"title":"基于90nm数字CMOS的5-b 1-GS/s 2.7 mw二值搜索ADC","authors":"Yung-Hui Chung, Cheng-Hsun Tsai, Hsuan-Chin Yeh","doi":"10.1109/SOCC.2015.7406902","DOIUrl":null,"url":null,"abstract":"A power-efficiency and speed-enhancing technique for binary-search ADCs is presented. Asynchronous timing and reduced-count binary-search architecture is implemented to achieve a high-speed operation. The distributed track-and-hold circuit is applied to relax the ENOB degradation caused by the comparator kickback noise and dynamic offset. A prototype 5-b 1-GS/s ADC was simulated in a 90nm CMOS technology. It consumes 2.7 mW from a 1.2 V supply. The ADC core occupies an active area of 0.012 mm2. With the post-layout simulation results, the SNDR and SFDR are 30 dB and 40 dB respectively. The equivalent ENOB is 4.55 b at the Nyquist-rate input. Its FoM is 115 fJ/conversion-step.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A 5-b 1-GS/s 2.7-mW binary-search ADC in 90nm digital CMOS\",\"authors\":\"Yung-Hui Chung, Cheng-Hsun Tsai, Hsuan-Chin Yeh\",\"doi\":\"10.1109/SOCC.2015.7406902\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A power-efficiency and speed-enhancing technique for binary-search ADCs is presented. Asynchronous timing and reduced-count binary-search architecture is implemented to achieve a high-speed operation. The distributed track-and-hold circuit is applied to relax the ENOB degradation caused by the comparator kickback noise and dynamic offset. A prototype 5-b 1-GS/s ADC was simulated in a 90nm CMOS technology. It consumes 2.7 mW from a 1.2 V supply. The ADC core occupies an active area of 0.012 mm2. With the post-layout simulation results, the SNDR and SFDR are 30 dB and 40 dB respectively. The equivalent ENOB is 4.55 b at the Nyquist-rate input. Its FoM is 115 fJ/conversion-step.\",\"PeriodicalId\":329464,\"journal\":{\"name\":\"2015 28th IEEE International System-on-Chip Conference (SOCC)\",\"volume\":\"69 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 28th IEEE International System-on-Chip Conference (SOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCC.2015.7406902\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 28th IEEE International System-on-Chip Conference (SOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC.2015.7406902","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 5-b 1-GS/s 2.7-mW binary-search ADC in 90nm digital CMOS
A power-efficiency and speed-enhancing technique for binary-search ADCs is presented. Asynchronous timing and reduced-count binary-search architecture is implemented to achieve a high-speed operation. The distributed track-and-hold circuit is applied to relax the ENOB degradation caused by the comparator kickback noise and dynamic offset. A prototype 5-b 1-GS/s ADC was simulated in a 90nm CMOS technology. It consumes 2.7 mW from a 1.2 V supply. The ADC core occupies an active area of 0.012 mm2. With the post-layout simulation results, the SNDR and SFDR are 30 dB and 40 dB respectively. The equivalent ENOB is 4.55 b at the Nyquist-rate input. Its FoM is 115 fJ/conversion-step.
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