400 gbit /s相干数据中心互连接收机的DSP和FEC的ASIC设计探索

2020 Optical Fiber Communications Conference and Exhibition (OFC) Pub Date : 2020-03-01 DOI:10.1364/ofc.2020.th2a.38

C. Fougstedt, O. Gustafsson, Cheolyong Bae, E. Börjeson, P. Larsson-Edefors

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引用次数: 11

摘要

对400 gbit /s相干数据中心互连接收机的关键DSP和FEC单元进行了探索性的ASIC设计。在22nm CMOS中，所考虑的单元总共消耗5W，这表明在功率受限的形状因素下实现是可行的。

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ASIC Design Exploration for DSP and FEC of 400-Gbit/s Coherent Data-Center Interconnect Receivers

We perform exploratory ASIC design of key DSP and FEC units for 400-Gbit/s coherent data-center interconnect receivers. In 22-nm CMOS, the considered units together dissipate 5W, suggesting implementation feasibility in power-constrained form factors.

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2020 Optical Fiber Communications Conference and Exhibition (OFC)

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