采用太赫兹光非对称解复用器的低成本乘法器电路的全光设计

Arpan Manna, Subham Saha, Rakesh Das, Chandan Bandyopadhyay, H. Rahaman
{"title":"采用太赫兹光非对称解复用器的低成本乘法器电路的全光设计","authors":"Arpan Manna, Subham Saha, Rakesh Das, Chandan Bandyopadhyay, H. Rahaman","doi":"10.1109/ISED.2017.8303945","DOIUrl":null,"url":null,"abstract":"In this work we present an efficient multiplication technique using terahertz optical asymmetric demultiplexer (TOAD) in all optical domain. Two approaches are presented here. The first model is a hierarchical design where we have shown a pipelined implementation of array multiplier for unsigned numbers. The second design is the improved design of the first one as it can work for both signed and unsigned numbers. Initially we have shown an n-bit model and afterwards illustrated it for a 4-bit circuit. In terms of design overhead, the second design is more than 50 percent cost efficient than the first one. Design analysis for both the models is presented in the later part of the work.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"177 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"All optical design of cost efficient multiplier circuit using terahertz optical asymmetric demultiplexer\",\"authors\":\"Arpan Manna, Subham Saha, Rakesh Das, Chandan Bandyopadhyay, H. Rahaman\",\"doi\":\"10.1109/ISED.2017.8303945\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work we present an efficient multiplication technique using terahertz optical asymmetric demultiplexer (TOAD) in all optical domain. Two approaches are presented here. The first model is a hierarchical design where we have shown a pipelined implementation of array multiplier for unsigned numbers. The second design is the improved design of the first one as it can work for both signed and unsigned numbers. Initially we have shown an n-bit model and afterwards illustrated it for a 4-bit circuit. In terms of design overhead, the second design is more than 50 percent cost efficient than the first one. Design analysis for both the models is presented in the later part of the work.\",\"PeriodicalId\":147019,\"journal\":{\"name\":\"2017 7th International Symposium on Embedded Computing and System Design (ISED)\",\"volume\":\"177 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 7th International Symposium on Embedded Computing and System Design (ISED)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISED.2017.8303945\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISED.2017.8303945","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

摘要

在这项工作中,我们提出了一种在全光域使用太赫兹光不对称解复用器(TOAD)的高效乘法技术。这里提出了两种方法。第一个模型是分层设计,其中我们展示了用于无符号数的数组乘法器的流水线实现。第二种设计是第一种设计的改进,因为它可以同时用于有符号和无符号的数字。首先,我们展示了一个n位模型,然后说明了它的4位电路。在设计开销方面,第二个设计比第一个设计节省了50%以上的成本。本文的后半部分将介绍两种模型的设计分析。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
All optical design of cost efficient multiplier circuit using terahertz optical asymmetric demultiplexer
In this work we present an efficient multiplication technique using terahertz optical asymmetric demultiplexer (TOAD) in all optical domain. Two approaches are presented here. The first model is a hierarchical design where we have shown a pipelined implementation of array multiplier for unsigned numbers. The second design is the improved design of the first one as it can work for both signed and unsigned numbers. Initially we have shown an n-bit model and afterwards illustrated it for a 4-bit circuit. In terms of design overhead, the second design is more than 50 percent cost efficient than the first one. Design analysis for both the models is presented in the later part of the work.
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