Power Attack on VHDL Implementation of Continuously Running Block Ciphers

The Correlation Power Analysis (CPA) is used to compromise the security of crypto systems by measuring and analyzing physical leakage that is the power consumption. Unlike classical cryptanalysis techniques, it requires very less computations to extract the secret information of the cipher systems. But, one of the main hindrances in mounting the CPA attack is the segregation of single power trace of multiple encryptions performed continuously (without pause) among number of traces corresponding to individual encryptions. To overcome this limitation, a new technique is proposed in this paper to split the power traces of AES and DES algorithms running continuously on FPGA. This (energy of samples based algorithm) finds the start of the encryption and computes number of samples in each clock of FPGA. It exploits the repetition of specific patterns available in the traces to determine the encryption length in terms of number of samples. With this information, it splits a power trace of several consecutive encryptions among number of traces corresponding to each encryption. The important thing is that it does not require information about clock frequency of FPGA board and sampling rate of the Oscilloscope. This algorithm was applied on the traces of 25, 50, 100, 125 and 250 samples per clock (when processing was performed at 1, 2 & 4 MHz clock frequencies). In all the cases, the key of AES and DES were retrieved by mounting the CPA attack on splitted traces resulting from the splitting technique.