Design and FPGA Implementation of an Islanding Detection cum Re-synchronisation Technique for a Grid Connected Inverter in a DC Microgrid

Proper detection of islanding of a microgrid and its resynchronisation is very important for the plug and play operation. A simple passive islanding detection and resynchronisation technique is proposed in this paper. The change in the voltage magnitude, frequency and phase are taken into the consideration to avoid any false triggering during the detection process. In addition, the proposed technique is designed in such a way that it can be implemented in a field-programmable gate array (FPGA) hardware using FPGA-in-Loop (FIL) platform. The complete controller is converted into VHDL, a hardware description language code. Finally, the bitstream generated from the code is implemented in FPGA hardware, Zedboard. The results obtained in terms of both islanding detection and resynchronisation using the FPGA-in-Loop simulation are found to be satisfactory.