具有双轨输入的绝热伪多米诺逻辑

Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257) Pub Date : 2001-08-14 DOI:10.1109/MWSCAS.2001.986182

H. Wong, K. Lau

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引用次数: 5

摘要

双轨逻辑的平衡评估支路不仅可以最大限度地降低功耗，而且可以提高电路的工作频率。在本文中，APDL系列采用了全双轨输入信号结构，尽管它增加了原电路中晶体管的数量。HSPICE仿真表明，DAPDL移位寄存器比其静态CMOS对口寄存器消耗的能量少6倍。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Adiabatic pseudo-domino logic with dual-rail inputs

Balanced evaluation branches for dual-rail logic are essential not only to minimize the power dissipation but also to improve the operating frequency of the circuit. In this paper, a fully dual-rail input signaling structure is adopted for the APDL family, even though it increases the number of the transistors in the original circuit. HSPICE simulation shows that DAPDL shift register dissipates 6 times lesser energy than its static CMOS counterpart.

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Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)

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