{"title":"自定义掩码布局的自顶向下技术迁移方法","authors":"Z. Apanovich, A. Marchuk","doi":"10.1109/ICVD.1998.646577","DOIUrl":null,"url":null,"abstract":"The approach to technology migration presented in this paper is based on a compaction and rerouting strategy. It takes as input the full-chip mask layout hierarchical description (CIF format) and produces as output the mask layout in the target design rules. The applicability of the compaction and rerouting facilities, and the flexibility of the routing layers redistribution between different levels of mask layout hierarchy, are provided by a procedure for mask layout decomposition. The decomposition procedure takes as input any node of the mask layout hierarchical description and extracts the fragments which should be transformed by means of compaction. The size of the extracted fragments is controlled by decomposition parameters. Each extracted fragment is processed by a symbolisation procedure which provides resizing and regeneration of elementary objects such as transistors, contacts and wires. The target mask layout for each fragment is generated by a compaction procedure which is controlled by the constraints extracted during the symbolisation step. The resulting chip mask layout is generated by a routing procedure which is controlled by the data structures (netlist and floorplan) extracted during the decomposition step.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"173 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Top-down approach to technology migration for full-custom mask layouts\",\"authors\":\"Z. Apanovich, A. Marchuk\",\"doi\":\"10.1109/ICVD.1998.646577\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The approach to technology migration presented in this paper is based on a compaction and rerouting strategy. It takes as input the full-chip mask layout hierarchical description (CIF format) and produces as output the mask layout in the target design rules. The applicability of the compaction and rerouting facilities, and the flexibility of the routing layers redistribution between different levels of mask layout hierarchy, are provided by a procedure for mask layout decomposition. The decomposition procedure takes as input any node of the mask layout hierarchical description and extracts the fragments which should be transformed by means of compaction. The size of the extracted fragments is controlled by decomposition parameters. Each extracted fragment is processed by a symbolisation procedure which provides resizing and regeneration of elementary objects such as transistors, contacts and wires. The target mask layout for each fragment is generated by a compaction procedure which is controlled by the constraints extracted during the symbolisation step. The resulting chip mask layout is generated by a routing procedure which is controlled by the data structures (netlist and floorplan) extracted during the decomposition step.\",\"PeriodicalId\":139023,\"journal\":{\"name\":\"Proceedings Eleventh International Conference on VLSI Design\",\"volume\":\"173 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-01-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings Eleventh International Conference on VLSI Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICVD.1998.646577\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Eleventh International Conference on VLSI Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICVD.1998.646577","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Top-down approach to technology migration for full-custom mask layouts
The approach to technology migration presented in this paper is based on a compaction and rerouting strategy. It takes as input the full-chip mask layout hierarchical description (CIF format) and produces as output the mask layout in the target design rules. The applicability of the compaction and rerouting facilities, and the flexibility of the routing layers redistribution between different levels of mask layout hierarchy, are provided by a procedure for mask layout decomposition. The decomposition procedure takes as input any node of the mask layout hierarchical description and extracts the fragments which should be transformed by means of compaction. The size of the extracted fragments is controlled by decomposition parameters. Each extracted fragment is processed by a symbolisation procedure which provides resizing and regeneration of elementary objects such as transistors, contacts and wires. The target mask layout for each fragment is generated by a compaction procedure which is controlled by the constraints extracted during the symbolisation step. The resulting chip mask layout is generated by a routing procedure which is controlled by the data structures (netlist and floorplan) extracted during the decomposition step.