Dual Scale Topology Opto-Electronic Processor (D-STOP): Comparative Analysis and Technological Feasibility

A variety of applications in artificial neural networks, interconnection networks, artificial intelligence, relational databases, and numerical processing require parallel, large scale implementations of matrix-algebraic architectures. Existing VLSI implementations of these architectures are restricted in terms of their parallelism and bandwidth due to their inherent connectivity, pin-out, power dissipation, and crosstalk limitations.[1,2] On the other hand, existing optical matrix-vector architectures suffer from limited SLM throughput and accuracy as well as limited functional flexibility. In the following sections we describe and analyze the Dual-Scale Topology OptoElectronic Processor (D-STOP)[3] which alleviates these limitations, and discuss its feasibility for a near-term implementation.