{"title":"基于WTM的组合测试向量和输出响应重排序,采用Dijkstra算法降低扫描功率","authors":"H. Parmar, S. Ruparelia, U. Mehta","doi":"10.1109/NUICONE.2011.6153276","DOIUrl":null,"url":null,"abstract":"Test power has become a serious problem with scan-based testing. It can lead to prohibitive test power in the process of test application. During the process of scan shifting, the states of the flip-flops are changing continually, which causes excessive switching activities. Test vector reordering for reducing scan in scan out power is one of the general goal of low power testing. In this paper Dijakstra algorithm is proposed to reorder the test vectors in an optimal manner to minimize switching activity during testing. Here, by passing the test vectors through output response a weighted transition matrix(WTM) is calculated, and then Dijkstra algorithm is applied which helps to reduce switching activities. The experimental results on ISCAS benchmark circuit proves that the proposed algorithm gives an average of 39.95% reduction in switching.","PeriodicalId":206392,"journal":{"name":"2011 Nirma University International Conference on Engineering","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"WTM based reordering of combine test vector & output response using Dijkstra algorithm for scan power reduction\",\"authors\":\"H. Parmar, S. Ruparelia, U. Mehta\",\"doi\":\"10.1109/NUICONE.2011.6153276\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Test power has become a serious problem with scan-based testing. It can lead to prohibitive test power in the process of test application. During the process of scan shifting, the states of the flip-flops are changing continually, which causes excessive switching activities. Test vector reordering for reducing scan in scan out power is one of the general goal of low power testing. In this paper Dijakstra algorithm is proposed to reorder the test vectors in an optimal manner to minimize switching activity during testing. Here, by passing the test vectors through output response a weighted transition matrix(WTM) is calculated, and then Dijkstra algorithm is applied which helps to reduce switching activities. The experimental results on ISCAS benchmark circuit proves that the proposed algorithm gives an average of 39.95% reduction in switching.\",\"PeriodicalId\":206392,\"journal\":{\"name\":\"2011 Nirma University International Conference on Engineering\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 Nirma University International Conference on Engineering\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NUICONE.2011.6153276\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 Nirma University International Conference on Engineering","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NUICONE.2011.6153276","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
WTM based reordering of combine test vector & output response using Dijkstra algorithm for scan power reduction
Test power has become a serious problem with scan-based testing. It can lead to prohibitive test power in the process of test application. During the process of scan shifting, the states of the flip-flops are changing continually, which causes excessive switching activities. Test vector reordering for reducing scan in scan out power is one of the general goal of low power testing. In this paper Dijakstra algorithm is proposed to reorder the test vectors in an optimal manner to minimize switching activity during testing. Here, by passing the test vectors through output response a weighted transition matrix(WTM) is calculated, and then Dijkstra algorithm is applied which helps to reduce switching activities. The experimental results on ISCAS benchmark circuit proves that the proposed algorithm gives an average of 39.95% reduction in switching.