{"title":"TFT电路的一些模拟构建块","authors":"R. Itou, M. Kayama, T. Shima","doi":"10.1109/MWSCAS.2001.986201","DOIUrl":null,"url":null,"abstract":"The analog circuits fabricated by the amorphous and/or polycrystalline silicon TFT suffer from very wide deviation effects of the threshold voltage Vth and the current gain /spl beta/. This paper proposes some analog building blocks for TFT circuits, in which the techniques to reduce the effects caused by the threshold voltage and the current gain /spl beta/ mismatch of the transistors are used. First, Vth and /spl beta/ deviation-free differential amplifier is discussed. Second, Vth deviation-free current source is proposed. Finally, Vth and /spl beta/ deviation-free class A amplifier is presented. The test chip to verify the proposed idea has been simulated and designed using VDEC design environment.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Some analog building blocks for TFT circuits\",\"authors\":\"R. Itou, M. Kayama, T. Shima\",\"doi\":\"10.1109/MWSCAS.2001.986201\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The analog circuits fabricated by the amorphous and/or polycrystalline silicon TFT suffer from very wide deviation effects of the threshold voltage Vth and the current gain /spl beta/. This paper proposes some analog building blocks for TFT circuits, in which the techniques to reduce the effects caused by the threshold voltage and the current gain /spl beta/ mismatch of the transistors are used. First, Vth and /spl beta/ deviation-free differential amplifier is discussed. Second, Vth deviation-free current source is proposed. Finally, Vth and /spl beta/ deviation-free class A amplifier is presented. The test chip to verify the proposed idea has been simulated and designed using VDEC design environment.\",\"PeriodicalId\":403026,\"journal\":{\"name\":\"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-08-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2001.986201\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2001.986201","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The analog circuits fabricated by the amorphous and/or polycrystalline silicon TFT suffer from very wide deviation effects of the threshold voltage Vth and the current gain /spl beta/. This paper proposes some analog building blocks for TFT circuits, in which the techniques to reduce the effects caused by the threshold voltage and the current gain /spl beta/ mismatch of the transistors are used. First, Vth and /spl beta/ deviation-free differential amplifier is discussed. Second, Vth deviation-free current source is proposed. Finally, Vth and /spl beta/ deviation-free class A amplifier is presented. The test chip to verify the proposed idea has been simulated and designed using VDEC design environment.