基于垂直高斯掺杂的功函数工程高k栅极堆叠DG MOSFET的短通道行为建模

2018 IEEE Electron Devices Kolkata Conference (EDKCON) Pub Date : 2018-11-01 DOI:10.1109/EDKCON.2018.8770421

Priyanka Saha, Pritha Banerjee, Dinesh Kumar Dash, S. Sarkar

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引用次数: 0

摘要

本文针对垂直高斯掺杂的工作函数工程(WFE)高k栅叠双栅MOSFET，建立了考虑泊松方程和表面电位最小值强反演准则的二维表面电位和阈值电压模型。从表面电位、电场、阈值电压性能和DIBL效应等方面探讨了器件特性，并与普通DG MOSFET进行了对比研究，以研究器件对不良短通道效应的抗扰度提升。将分析模型的结果与ATLAS仿真数据进行了比较，验证了推导模型的正确性。

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Modeling Short Channel Behavior of Proposed Work Function Engineered High-k Gate Stack DG MOSFET with Vertical Gaussian Doping

In this paper, 2D surface potential and threshold voltage model considering Poisson's equation and strong inversion criterion at surface potential minima is derived for our proposed work function engineered (WFE) high-k gate stack double gate (DG) MOSFET with vertical Gaussian doping. The device characteristics are explored in terms of surface potential, electric field, threshold voltage performance and DIBL effect along with comparative study with its normal DG MOSFET counterpart to investigate the upgraded immunity of the device to undesirable short channel effects. Results of analytical model are compared with ATLAS simulation data to validate our present derived model.

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2018 IEEE Electron Devices Kolkata Conference (EDKCON)

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