基于FPGA的DDS-ADPLL传感器谐振频率跟踪的设计与实现

Mohd Ziauddin Jahangir, P. Chandra Sekhar, M. Sikander, J. V. Krishna
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摘要

本文介绍了用于谐振传感器的正弦波DDS-全数字锁相环的设计和FPGA实现。由机械结构组成的传感器。所提出的锁相环设计用于跟踪机械结构在不同空间取向下的谐振频率变化。被测机械结构的期望谐振频率小于10khz。由于大多数CMOS锁相环ic工作在非常高的频率,它不适合在这种应用中使用。此外,锁相环的数字实现是首选,因为它具有高度的可配置性。本文介绍了两种不同正弦波DDS adpll的结构和设计。采用SPI adc和dac接口,在FPGA上实现了1型正弦波DDS ADPLL。本文还介绍了在硬件上实现ADPLL的重要设计考虑。所实现的ADPLL在7KHz中心频率附近具有良好的锁定性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design and Implementation of FPGA based DDS-ADPLL for Resonant Frequency Tracking in Sensors
This work presents the design and FPGA implementation of a Sine-Wave DDS- All-Digital PLLs for resonant sensors application. The sensor consisting of a mechanical structure. The proposed PLL was designed to track changes in the resonant frequency of a mechanical structure under different spatial orientations. The expected resonant frequency of the mechanical structure under test is less than 10 KHz. As most CMOS PLL ICs operate at very high frequencies, it is not suitable to be used in this application. Additionally, a digital implementation of PLL is preferred due it’s high degree of configurability. In this work, the architecture and design of two different sine wave DDS ADPLLs are presented. A Type-1 sine wave DDS ADPLL was realized on FPGA using SPI ADCs & DACs for interfacing. The important design considerations for realizing proposed ADPLL on the hardware are also presented in this work. The realized ADPLL exhibited a perfect locking behavior around 7KHz center frequency.
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