Nicky Lu, C. Shiah, Juang-Ying Chueh, B. Rong, Wei-Jr Huang, Ho-Yin Chen, Cheng-Nan Chang, C. Chang, Tzung-Shen Chen
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Enhanced Core Circuits for scaling DRAM: 0.7V VCC with Long Retention 138ms at 125°C and Random Row/Column Access Times Accelerated by 1.5ns
Two inventions improve DRAM’s core circuits within a 1Gb DDR3 product: (1) Scale VCC down to 0.7V but generate a Restore ONE signal 1.3V into memory cells to enhance Retention-Time at least to 138ms at 125°C. This facilitates scaling VDD and peripheral devices. (2) When addresses are ready in the DRAM-controller, an Interface Circuitry enables pre-decoding Row/Column addresses into the DRAM before other Commands, thus accelerating Random-Access Row/Column Times by 1.5ns, respectively.
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