{"title":"28nm CMOS制程防误触发的高效率电源轨ESD箝位电路","authors":"Zilong Shen, Yize Wang, Xing Zhang, Yuan Wang","doi":"10.1109/EDTM53872.2022.9798142","DOIUrl":null,"url":null,"abstract":"In this work, a new power-rail electrostatic discharge (ESD) clamp circuit with hybrid triggering mechanism is proposed and implemented in a 28-nm CMOS process. Measurements from silicon chips show that the proposed area-efficient power clamp circuit is capable of achieving μs-level transient response time with an RC time constant of 10 ns and avoiding triggering under fast power-on conditions. In addition, the circuit also has low standby leakage current under normal power-on conditions.","PeriodicalId":158478,"journal":{"name":"2022 6th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Area-efficient Power-rail ESD Clamp Circuit with False-trigger Immunity in 28nm CMOS Process\",\"authors\":\"Zilong Shen, Yize Wang, Xing Zhang, Yuan Wang\",\"doi\":\"10.1109/EDTM53872.2022.9798142\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work, a new power-rail electrostatic discharge (ESD) clamp circuit with hybrid triggering mechanism is proposed and implemented in a 28-nm CMOS process. Measurements from silicon chips show that the proposed area-efficient power clamp circuit is capable of achieving μs-level transient response time with an RC time constant of 10 ns and avoiding triggering under fast power-on conditions. In addition, the circuit also has low standby leakage current under normal power-on conditions.\",\"PeriodicalId\":158478,\"journal\":{\"name\":\"2022 6th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)\",\"volume\":\"64 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-03-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 6th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDTM53872.2022.9798142\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 6th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDTM53872.2022.9798142","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Area-efficient Power-rail ESD Clamp Circuit with False-trigger Immunity in 28nm CMOS Process
In this work, a new power-rail electrostatic discharge (ESD) clamp circuit with hybrid triggering mechanism is proposed and implemented in a 28-nm CMOS process. Measurements from silicon chips show that the proposed area-efficient power clamp circuit is capable of achieving μs-level transient response time with an RC time constant of 10 ns and avoiding triggering under fast power-on conditions. In addition, the circuit also has low standby leakage current under normal power-on conditions.
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