{"title":"优化了高密度eDRAM的信号传输方案","authors":"Xinhong Hong, L. Pan, Haozhi Ma, Dong Wu, Jun Xu","doi":"10.1109/ISNE.2016.7543284","DOIUrl":null,"url":null,"abstract":"In this work, optimized signal transmission schemes are proposed to improve the signal transmission speed and area efficiency of high density embedded DRAM (eDRAM). As in the schemes, overdrive scheme is adopted to enhance the drive capability of read word-line (RWL) inverters and reduce inverters area overhead, optimized signal transmission path scheme is proposed to reduce signal transmission loading, and a Vth loss compensation and signal path pre-charge technology are also adopted to improve the data access speed. The proposed schemes are implemented in 1Mb eDRAM on 65nm CMOS technology node. Calculation and simulation results present 20% area reduction on RWL pull-down inverters and 10% data access speed improvement.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"183 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Optimized signal transmission schemes for high density eDRAM\",\"authors\":\"Xinhong Hong, L. Pan, Haozhi Ma, Dong Wu, Jun Xu\",\"doi\":\"10.1109/ISNE.2016.7543284\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work, optimized signal transmission schemes are proposed to improve the signal transmission speed and area efficiency of high density embedded DRAM (eDRAM). As in the schemes, overdrive scheme is adopted to enhance the drive capability of read word-line (RWL) inverters and reduce inverters area overhead, optimized signal transmission path scheme is proposed to reduce signal transmission loading, and a Vth loss compensation and signal path pre-charge technology are also adopted to improve the data access speed. The proposed schemes are implemented in 1Mb eDRAM on 65nm CMOS technology node. Calculation and simulation results present 20% area reduction on RWL pull-down inverters and 10% data access speed improvement.\",\"PeriodicalId\":127324,\"journal\":{\"name\":\"2016 5th International Symposium on Next-Generation Electronics (ISNE)\",\"volume\":\"183 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-05-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 5th International Symposium on Next-Generation Electronics (ISNE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISNE.2016.7543284\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISNE.2016.7543284","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Optimized signal transmission schemes for high density eDRAM
In this work, optimized signal transmission schemes are proposed to improve the signal transmission speed and area efficiency of high density embedded DRAM (eDRAM). As in the schemes, overdrive scheme is adopted to enhance the drive capability of read word-line (RWL) inverters and reduce inverters area overhead, optimized signal transmission path scheme is proposed to reduce signal transmission loading, and a Vth loss compensation and signal path pre-charge technology are also adopted to improve the data access speed. The proposed schemes are implemented in 1Mb eDRAM on 65nm CMOS technology node. Calculation and simulation results present 20% area reduction on RWL pull-down inverters and 10% data access speed improvement.