{"title":"一个容错的二维排序网络","authors":"J. Krammer, H. Arif","doi":"10.1109/ASAP.1990.145469","DOIUrl":null,"url":null,"abstract":"The authors evaluate a class of sorting algorithms which can be adapted to a faulty network with nearest neighbor interconnections by determining a suitable indexing scheme. A worst case sorting time of O(N) is proved for these sorters. Simulation results show that the average sorting time of the fault-tolerant sorters is only slightly higher than O( square root N), and therefore is comparable to that of non-fault-tolerant sorting algorithms. This algorithmic approach does not require additional wiring for reconfiguration, and hence the amount of additional circuitry required for fault-tolerance is very small. An efficient procedure for calculating an indexing scheme is presented and simulation results are shown. Furthermore, an efficient strategy for testing the network is proposed.<<ETX>>","PeriodicalId":438078,"journal":{"name":"[1990] Proceedings of the International Conference on Application Specific Array Processors","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A fault-tolerant two-dimensional sorting network\",\"authors\":\"J. Krammer, H. Arif\",\"doi\":\"10.1109/ASAP.1990.145469\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors evaluate a class of sorting algorithms which can be adapted to a faulty network with nearest neighbor interconnections by determining a suitable indexing scheme. A worst case sorting time of O(N) is proved for these sorters. Simulation results show that the average sorting time of the fault-tolerant sorters is only slightly higher than O( square root N), and therefore is comparable to that of non-fault-tolerant sorting algorithms. This algorithmic approach does not require additional wiring for reconfiguration, and hence the amount of additional circuitry required for fault-tolerance is very small. An efficient procedure for calculating an indexing scheme is presented and simulation results are shown. Furthermore, an efficient strategy for testing the network is proposed.<<ETX>>\",\"PeriodicalId\":438078,\"journal\":{\"name\":\"[1990] Proceedings of the International Conference on Application Specific Array Processors\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-09-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1990] Proceedings of the International Conference on Application Specific Array Processors\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASAP.1990.145469\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1990] Proceedings of the International Conference on Application Specific Array Processors","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASAP.1990.145469","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The authors evaluate a class of sorting algorithms which can be adapted to a faulty network with nearest neighbor interconnections by determining a suitable indexing scheme. A worst case sorting time of O(N) is proved for these sorters. Simulation results show that the average sorting time of the fault-tolerant sorters is only slightly higher than O( square root N), and therefore is comparable to that of non-fault-tolerant sorting algorithms. This algorithmic approach does not require additional wiring for reconfiguration, and hence the amount of additional circuitry required for fault-tolerance is very small. An efficient procedure for calculating an indexing scheme is presented and simulation results are shown. Furthermore, an efficient strategy for testing the network is proposed.<>