{"title":"用于下一代数据处理电路的低压板载DC/DC模块的设计考虑","authors":"M.T. Zhang, M. Jovanovic, F. Lee","doi":"10.1109/PEDS.1995.404890","DOIUrl":null,"url":null,"abstract":"By reducing the power supply voltage, a higher speed, lower power consumption, and higher integration density of data processing ICs can be achieved. A variety of ICs operating from 3.3 V are available. Next generations of ICs are expected to work even with lower voltages, i.e., in the 1-3 V range, to further enhance their speed-power performance. At the same time, during transients these new generations of data ICs will present very dynamic loads with high current slew rates. As a result, they will require point-of-load power supplies in order to minimize the effects of the interconnection parasitics. These on-board power supplies will be derived from the existing voltages available in the system (usually 5 V or 12 V), and will be required to have high power densities, high efficiencies, and good transient performance. This paper presents design considerations for these on-board power supplies and discusses their performance limits imposed by various circuit and system parasitics.<<ETX>>","PeriodicalId":244042,"journal":{"name":"Proceedings of 1995 International Conference on Power Electronics and Drive Systems. PEDS 95","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-02-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"196","resultStr":"{\"title\":\"Design considerations for low-voltage on-board DC/DC modules for next generations of data processing circuits\",\"authors\":\"M.T. Zhang, M. Jovanovic, F. Lee\",\"doi\":\"10.1109/PEDS.1995.404890\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"By reducing the power supply voltage, a higher speed, lower power consumption, and higher integration density of data processing ICs can be achieved. A variety of ICs operating from 3.3 V are available. Next generations of ICs are expected to work even with lower voltages, i.e., in the 1-3 V range, to further enhance their speed-power performance. At the same time, during transients these new generations of data ICs will present very dynamic loads with high current slew rates. As a result, they will require point-of-load power supplies in order to minimize the effects of the interconnection parasitics. These on-board power supplies will be derived from the existing voltages available in the system (usually 5 V or 12 V), and will be required to have high power densities, high efficiencies, and good transient performance. This paper presents design considerations for these on-board power supplies and discusses their performance limits imposed by various circuit and system parasitics.<<ETX>>\",\"PeriodicalId\":244042,\"journal\":{\"name\":\"Proceedings of 1995 International Conference on Power Electronics and Drive Systems. PEDS 95\",\"volume\":\"33 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-02-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"196\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 1995 International Conference on Power Electronics and Drive Systems. PEDS 95\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/PEDS.1995.404890\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1995 International Conference on Power Electronics and Drive Systems. PEDS 95","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PEDS.1995.404890","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design considerations for low-voltage on-board DC/DC modules for next generations of data processing circuits
By reducing the power supply voltage, a higher speed, lower power consumption, and higher integration density of data processing ICs can be achieved. A variety of ICs operating from 3.3 V are available. Next generations of ICs are expected to work even with lower voltages, i.e., in the 1-3 V range, to further enhance their speed-power performance. At the same time, during transients these new generations of data ICs will present very dynamic loads with high current slew rates. As a result, they will require point-of-load power supplies in order to minimize the effects of the interconnection parasitics. These on-board power supplies will be derived from the existing voltages available in the system (usually 5 V or 12 V), and will be required to have high power densities, high efficiencies, and good transient performance. This paper presents design considerations for these on-board power supplies and discusses their performance limits imposed by various circuit and system parasitics.<>