{"title":"离散小波变换在实时图像压缩中的高效VLSI结构实现","authors":"A. Hashad, K. Shehata, S. Gasser","doi":"10.1109/ICEEC.2004.1374566","DOIUrl":null,"url":null,"abstract":"The discrete wavelet transforms is used as a forward transform in the JPEG2000 standard for still image compression. An eflcient VLSI architecture is presented and its performance is evaluated and compared to the previously proposed architectures. This architecture is functionally simulated and synthesized on two dserent types of FPGA chips, the design statistics and dynamic performance (maximum switching frequency) turned out to be practically feasible.","PeriodicalId":180043,"journal":{"name":"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Realization of an efficient VLSI architecture for discrete wavelet transform in real time image compression\",\"authors\":\"A. Hashad, K. Shehata, S. Gasser\",\"doi\":\"10.1109/ICEEC.2004.1374566\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The discrete wavelet transforms is used as a forward transform in the JPEG2000 standard for still image compression. An eflcient VLSI architecture is presented and its performance is evaluated and compared to the previously proposed architectures. This architecture is functionally simulated and synthesized on two dserent types of FPGA chips, the design statistics and dynamic performance (maximum switching frequency) turned out to be practically feasible.\",\"PeriodicalId\":180043,\"journal\":{\"name\":\"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.\",\"volume\":\"2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-09-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICEEC.2004.1374566\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEEC.2004.1374566","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Realization of an efficient VLSI architecture for discrete wavelet transform in real time image compression
The discrete wavelet transforms is used as a forward transform in the JPEG2000 standard for still image compression. An eflcient VLSI architecture is presented and its performance is evaluated and compared to the previously proposed architectures. This architecture is functionally simulated and synthesized on two dserent types of FPGA chips, the design statistics and dynamic performance (maximum switching frequency) turned out to be practically feasible.