在Vds = -1 V下具有高性能的CVD单层钨基PMOS晶体管

2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2022-10-28 DOI:10.1109/ICTA56932.2022.9963068

Xin Wang, Yanqing Wu

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引用次数: 1

摘要

二维(2D)半导体材料通道能够实现晶体管的最终缩放，并将在几十年内帮助摩尔定律缩放。在本文中，我们报道了用熔盐辅助化学气相沉积的方法，使用单层(- 0.85 nm)通道制备p型wse2晶体管。在单层p-WSe2晶体管中，基于100 nm SiO2/Si衬底制备的无转移后门器件在Vds= -1 V处具有最高的导通电流，且导通比高达108。

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CVD Monolayer tungsten-based PMOS Transistor with high performance at Vds = -1 V

Two-dimensional (2D) semiconducting materials channels enable ultimate scaling of transistors and will help Moore's Law Scaling for decades. In this paper, we reported p-type WSe2transistors using monolayer (¬0.85 nm) channels by molten-salt-assisted chemical vapor deposition. The transfer-free back-gate devices fabricated based on 100 nm SiO2/Si substrate exhibit highest on current at Vds= -1 V among transistors of monolayer p-WSe2, and a high on/off ratio up to 108.

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来源期刊

2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)

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