A. Amghayrir, P. Bréhonnet, N. Tanguy, P. Vilbé, L. Calvez, F. Huret
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A frequency domain approach for efficient model reduction of mixed VLSI circuits
It has become well accepted that interconnect delay dominates gate delay in current VLSI circuits. This paper introduces a new method, based on a frequency domain approach, for the simulation of interconnect problems found in high speed digital circuits and SOC-AMS.
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