{"title":"双分辨率全数字频率合成器","authors":"Y. Chau, Ying-Yuan Yang, Jeng-Fan Chen","doi":"10.1109/ISPACS.2006.364735","DOIUrl":null,"url":null,"abstract":"Based on the flying-adder structure, an all-digital frequency synthesizer with dual resolutions is designed and implemented. The range of the output frequencies of the all-digital frequency synthesizer is analyzed. The devised frequency synthesizer with dual resolutions is realized using the UMC 0.18- mum cell-based CMOS process. Corresponding simulation results and realization performance are presented.","PeriodicalId":178644,"journal":{"name":"2006 International Symposium on Intelligent Signal Processing and Communications","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"All-Digital Frequency Synthesizer with Dual Resolutions\",\"authors\":\"Y. Chau, Ying-Yuan Yang, Jeng-Fan Chen\",\"doi\":\"10.1109/ISPACS.2006.364735\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Based on the flying-adder structure, an all-digital frequency synthesizer with dual resolutions is designed and implemented. The range of the output frequencies of the all-digital frequency synthesizer is analyzed. The devised frequency synthesizer with dual resolutions is realized using the UMC 0.18- mum cell-based CMOS process. Corresponding simulation results and realization performance are presented.\",\"PeriodicalId\":178644,\"journal\":{\"name\":\"2006 International Symposium on Intelligent Signal Processing and Communications\",\"volume\":\"2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 International Symposium on Intelligent Signal Processing and Communications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPACS.2006.364735\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 International Symposium on Intelligent Signal Processing and Communications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPACS.2006.364735","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
All-Digital Frequency Synthesizer with Dual Resolutions
Based on the flying-adder structure, an all-digital frequency synthesizer with dual resolutions is designed and implemented. The range of the output frequencies of the all-digital frequency synthesizer is analyzed. The devised frequency synthesizer with dual resolutions is realized using the UMC 0.18- mum cell-based CMOS process. Corresponding simulation results and realization performance are presented.