Primitive-level pipelining method on delay-insensitive model for RSFQ pulse-driven logic

We present a primitive-level pipelining method in rapid single-flux-quantum (RSFQ) technology. In RSFQ circuits, binary information is represented by discrete voltage pulses unlike voltage levels in CMOS and related circuits. The method utilizes inherent storage capability in RSFQ primitives as pipeline registers. We propose a new RSFQ primitive that carries out a binary operation, holds the result, and controls the output. As the three tasks are performed in one primitive, it is expected to eliminate interconnect delays that are inevitable if three separate primitives are used. Data is transferred following a request-acknowledgment protocol in a delay-insensitive (DI) fashion. Due to delay insensitivity, high modularity is achieved. As examples, several adders and an array multiplier are designed on the DI model. We confirm the correctness of the circuit designs using a verification tool.