用于高速无线系统产品/应用测试的兼容多通道多频率串行误码率测试仪(BERT) ASIC IP核的HDL设计体系结构

P. Sastry, D. Rao, S. Vathsal, A. Rajaiah
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引用次数: 1

摘要

目的是实现兼容串行误码率测试仪SOC和基于多速率多通道PRBS序列的串行BERT IP核的RTL设计架构,用于高速无线串行通信数据采集SOC收发器产品和应用(3G, 4G, GPS, GSM, CDMA, WIFI, GIFI等)。不同PRBS模式序列的数据检验-2e7- 1,2e10 - 1,2e15 - 1,2e23 -1, 2e31-1。基本上,这个串行BERT由位于发射机侧的PRBS发生器模块组成,发送伪随机脉冲信号,通过串行链路传输。第二个模块位于接收器中产生相同的信号并与发射信号进行比较,如果有任何错误,如位滑、位误差、加性高斯白噪声(AWGN),则可以检测到错误的数量,并通过BERT核心对这些错误进行评估,估计错误率w.r.t比特数。采用VHDL和Verilog HDL进行软过程描述设计,采用Xilinx ISE软件设计工具进行仿真与综合设计,采用FPGA Spartan Development Kit进行测试与调试。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
HDL Design Architecture for Compatible Multichannel Multi-frequency Rate SERIAL Bit Error Rate Tester (BERT) ASIC IP Core for Testing of High Speed Wireless System Products/Applications
The Aim is to Implement RTL Design Architecture for Compatible Serial Bit Error Rate Tester SOC& Multi rate Multichannel PRBS Sequence Based SERIAL BERT IP Core for High Speed Wireless Serial Communication Data Acquisition SOC Transceiver Products & Applications (3G, 4G, GPS, GSM, CDMA, WIFI, GIFI etc). Testing of Data Done By Different PRBS Pattern Sequences-2e7-1, 2e10-1, 2e15-1, 2e23-1, 2e31-1. Basically this Serial BERT Consists of PRBS Generator Module located in the Transmitter Side & sends Pseudo Random Pulse signal is transmitted by the Serial link. Second Module is located in the receiver generate the same signal & compare with the transmitted signal, if any errors, like bit slip, bit error, Additive white Gaussian noise (AWGN), can then be detect the number of errors, and these errors are evaluated by the BERT core, estimate the error rate w.r.t number of bits. Design implementation through Soft Process Description using VHDL & Verilog HDL, Simulation & Synthesis of design done by Xilinx ISE Software Design Tool, Testing & Debugging done by FPGA Spartan Development Kit.
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