{"title":"具有自适应偏置电路的高效24ghz CMOS线性功率放大器","authors":"Hyunji Koo, Bonhoon Koo, Songcheol Hong","doi":"10.1109/APMC.2012.6421480","DOIUrl":null,"url":null,"abstract":"A 24 GHz Power amplifier (PA) with high efficiency designed in the 0.13-μm CMOS process is presented. The proposed adaptive-bias circuit is used to improve the efficiency. The quiescent power consumption is 79.2 mW, which is improved by 53.8mW, compared to that of the optimized fixed-biased (0.6V) PA. Power added efficiency (PAE) and output power (POUT) at a 1-dB-gain-compression-power (P1dB) is 15.6 % and 13.3 dBm, respectively. This result is improved as much as 4% and 1.2dB, compare to that of PA with fixed-bias of 0.6V.","PeriodicalId":359125,"journal":{"name":"2012 Asia Pacific Microwave Conference Proceedings","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"Highly efficient 24-GHz CMOS linear power amplifier with an adaptive bias circuit\",\"authors\":\"Hyunji Koo, Bonhoon Koo, Songcheol Hong\",\"doi\":\"10.1109/APMC.2012.6421480\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 24 GHz Power amplifier (PA) with high efficiency designed in the 0.13-μm CMOS process is presented. The proposed adaptive-bias circuit is used to improve the efficiency. The quiescent power consumption is 79.2 mW, which is improved by 53.8mW, compared to that of the optimized fixed-biased (0.6V) PA. Power added efficiency (PAE) and output power (POUT) at a 1-dB-gain-compression-power (P1dB) is 15.6 % and 13.3 dBm, respectively. This result is improved as much as 4% and 1.2dB, compare to that of PA with fixed-bias of 0.6V.\",\"PeriodicalId\":359125,\"journal\":{\"name\":\"2012 Asia Pacific Microwave Conference Proceedings\",\"volume\":\"37 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 Asia Pacific Microwave Conference Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APMC.2012.6421480\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 Asia Pacific Microwave Conference Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APMC.2012.6421480","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Highly efficient 24-GHz CMOS linear power amplifier with an adaptive bias circuit
A 24 GHz Power amplifier (PA) with high efficiency designed in the 0.13-μm CMOS process is presented. The proposed adaptive-bias circuit is used to improve the efficiency. The quiescent power consumption is 79.2 mW, which is improved by 53.8mW, compared to that of the optimized fixed-biased (0.6V) PA. Power added efficiency (PAE) and output power (POUT) at a 1-dB-gain-compression-power (P1dB) is 15.6 % and 13.3 dBm, respectively. This result is improved as much as 4% and 1.2dB, compare to that of PA with fixed-bias of 0.6V.
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