2xVDD数字输出缓冲器对工艺和电压变化不敏感

2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Pub Date : 2017-10-01 DOI:10.1109/PRIMEASIA.2017.8280356

Chua-Chin Wang, Pang-Yen Lou, Tsung-Yi Tsai, Yu-Lin Deng, Tzung-Je Lee

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引用次数: 1

摘要

提出了一种具有过程和电压补偿技术的2xVDD输出缓冲器，无论PV变化如何，都可以将摆压率(SR)保持在预定义范围内。本文没有考虑温度变化的原因，因为在90 nm或更好的工艺中，温度变化与转换率的相关性相对较低。过程和电压变化检测器中的所有偏置电压都是由带隙电路产生的，因此通过模拟可以保证变化在小于4.10%的范围内。通过物理测量，在1.0/2.0 V电源电压和20pf负载下，数据速率分别为650/ 500mhz。当所提出的光伏补偿设计被激活时，1× VDD和2× VDD的Δ SR分别提高了30.7%和31.4%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2xVDD digital output buffer insensitive to process and voltage variations

A 2xVDD output buffer with process and voltage (PV) compensation technique is proposed to keep slew rate (SR) within predefined ranges regardless PV variations. The reason of temperature variation is not considered is that it is found to be relatively low correlated to slew rate for 90 nm process or better. All bias voltages in process and voltage variation detectors are generated from bandgap circuits such that variations have been guaranteed by simulation within less than 4.10%. The data rate is 650/500 MHz given 1.0/2.0 V supply voltage with 20 pF load, respectively, by physical measurements. The Δ SR improvement is 30.7% and 31.4% for 1× VDD and 2× VDD, respectively, when the proposed PV compensation design is activated.

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来源期刊

2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)

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