全搜索块匹配算法的缓冲区大小优化

Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors Pub Date : 1997-07-14 DOI:10.1109/ASAP.1997.606814

Yuan-Hau Yeh, Chen-Yi Lee

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引用次数: 37

摘要

本文介绍了如何为全搜索块匹配算法的VLSI架构找到最优的缓冲区大小。从DG(依赖性图)分析出发，重点研究在最小I/O带宽约束下减小内部缓冲区大小的问题。为此，导出了一套系统的缓冲器优化设计程序，以降低实现成本。

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Buffer size optimization for full-search block matching algorithms

This paper presents how to find optimized buffer size for VLSI architectures of full-search block matching algorithms. Starting from the DG (dependency graph) analysis, we focus in the problem of reducing the internal buffer size under minimal I/O bandwidth constraint. As a result, a systematic design procedure for buffer optimization is derived to reduce realization cost.

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Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors

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