{"title":"具有中等风扇输入的电路","authors":"P. Hrubes, Anup Rao","doi":"10.4230/LIPIcs.CCC.2015.381","DOIUrl":null,"url":null,"abstract":"We consider boolean circuits in which every gate may compute an arbitrary boolean function of k other gates, for a parameter k. We give an explicit function f : {0, 1}n → {0, 1} that requires at least Ω(log2 n) non-input gates when k = 2n/3. When the circuit is restricted to being layered and depth 2, we prove a lower bound of nΩ(1) on the number of non-input gates. When the circuit is a formula with gates of fan-in k, we give a lower bound Ω(n2/k log n) on the total number of gates. \n \nOur model is connected to some well known approaches to proving lower bounds in complexity theory. Optimal lower bounds for the Number-On-Forehead model in communication complexity, or for bounded depth circuits in AC0, or extractors for varieties over small fields would imply strong lower bounds in our model. On the other hand, new lower bounds for our model would prove new time-space tradeoffs for branching programs and impossibility results for (fan-in 2) circuits with linear size and logarithmic depth. In particular, our lower bound gives a different proof for a known time-space tradeoff for oblivious branching programs.","PeriodicalId":246506,"journal":{"name":"Cybersecurity and Cyberforensics Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"21","resultStr":"{\"title\":\"Circuits with Medium Fan-In\",\"authors\":\"P. Hrubes, Anup Rao\",\"doi\":\"10.4230/LIPIcs.CCC.2015.381\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We consider boolean circuits in which every gate may compute an arbitrary boolean function of k other gates, for a parameter k. We give an explicit function f : {0, 1}n → {0, 1} that requires at least Ω(log2 n) non-input gates when k = 2n/3. When the circuit is restricted to being layered and depth 2, we prove a lower bound of nΩ(1) on the number of non-input gates. When the circuit is a formula with gates of fan-in k, we give a lower bound Ω(n2/k log n) on the total number of gates. \\n \\nOur model is connected to some well known approaches to proving lower bounds in complexity theory. Optimal lower bounds for the Number-On-Forehead model in communication complexity, or for bounded depth circuits in AC0, or extractors for varieties over small fields would imply strong lower bounds in our model. On the other hand, new lower bounds for our model would prove new time-space tradeoffs for branching programs and impossibility results for (fan-in 2) circuits with linear size and logarithmic depth. In particular, our lower bound gives a different proof for a known time-space tradeoff for oblivious branching programs.\",\"PeriodicalId\":246506,\"journal\":{\"name\":\"Cybersecurity and Cyberforensics Conference\",\"volume\":\"12 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-06-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"21\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Cybersecurity and Cyberforensics Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.4230/LIPIcs.CCC.2015.381\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Cybersecurity and Cyberforensics Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.4230/LIPIcs.CCC.2015.381","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 21
摘要
我们考虑布尔电路,其中每个门可以计算k个其他门的任意布尔函数,对于参数k。我们给出一个显式函数f: {0,1}n→{0,1},当k = 2n/3时,至少需要Ω(log2 n)个非输入门。当电路被限制为分层且深度为2时,我们证明了非输入门数量的下界nΩ(1)。当电路是一个有扇入k门的公式时,我们给出了门总数的下界Ω(n2/k log n)。我们的模型与一些众所周知的证明复杂性理论下界的方法有关。对于通信复杂度的number - on -额头模型,或者AC0中的有界深度电路,或者小域上的变量提取器,我们的模型中都有较强的下界。另一方面,我们模型的新下界将证明分支程序的新时空权衡,以及具有线性尺寸和对数深度的(扇入2)电路的不可能结果。特别是,我们的下界给出了一个不同的证明,证明了一个已知的时间-空间权衡对于无关分支程序。
We consider boolean circuits in which every gate may compute an arbitrary boolean function of k other gates, for a parameter k. We give an explicit function f : {0, 1}n → {0, 1} that requires at least Ω(log2 n) non-input gates when k = 2n/3. When the circuit is restricted to being layered and depth 2, we prove a lower bound of nΩ(1) on the number of non-input gates. When the circuit is a formula with gates of fan-in k, we give a lower bound Ω(n2/k log n) on the total number of gates.
Our model is connected to some well known approaches to proving lower bounds in complexity theory. Optimal lower bounds for the Number-On-Forehead model in communication complexity, or for bounded depth circuits in AC0, or extractors for varieties over small fields would imply strong lower bounds in our model. On the other hand, new lower bounds for our model would prove new time-space tradeoffs for branching programs and impossibility results for (fan-in 2) circuits with linear size and logarithmic depth. In particular, our lower bound gives a different proof for a known time-space tradeoff for oblivious branching programs.