A complete solution for Board-Level Signal Integrity Analysis Using IBIS Models

In this work the IBIS is employed to estimate the adverse effects of package wheresome modifications in its representation are proposed. IBIS is a standard file type which is widely popular in system design level. Many vendors, designers, and circuit simulators produce, use, and accept this standard nowadays. It represents the behavior of the I/O buffer of digital circuit considering their package parasitic effects. Our modifications on IBIS give rise to be better understanding of the package and digital I/O. The different conventional packages are tested considering wire connection between two chips. The effects of package and I/O, in companion with wire delay, overshoot, and undershoot on signal transition, are studied. The parasitic adverse effect of package can be as high as 41% for propagation delay and 38% for overshoot voltage.