FPGA Implementation of Multiplier-Accumulator Unit using Vedic multiplier and Reversible gates

The design of Multiplier-Accumulator (MAC) unit can be implemented by using the Vedic multiplier along with the reversible logic gates. The designing of Vedic multiplier is designed by using the new sutra called “Urdhava Triyagbhayam”. The performance of the MAC operation depends on the multiplier unit and the adder units. Here the designing of a multiplier and an adder can be designed by using the reversible gates to get the high speed of operation and also a Vedic multiplier is used for the higher performance, lesser area and to reduce the partial products. Nowadays reversible computing will take a more preferable for low power dissipation, higher speed of operation. Here, we proposed an 8, 16, 32, 64-bit Vedic multiplier is designed by using the carry save adder(CSA), the kogge stone adder(KSA) and the DKG adder out of these the proposed DKG gate adder is having the high speed of operation. The comparative analysis is carried out among the ripple carry adder (RCA), carry save adder, kogge stone adder. Finally, it has been proved that the proposed DKG gate with Vedic multiplier-adder is having the high speed of operation. The overall Simulation and synthesis process is carried out with Xilinx ISE 14.7 and is dumped on the FPGA Zynq board.