数字合成系统的VHDL实现

1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings Pub Date : 1995-11-06 DOI:10.1109/TENCON.1995.496409

L. Ng, C.C. Jong

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引用次数: 0

摘要

本文提出了一个用VHDL实现综合数字设计的软件系统，使设计能够被现有的CAD系统所接受，从而实现各种技术的延迟分析、逻辑仿真等低级验证和版图实现。

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Implementation of synthesized digital systems with VHDL

This paper presents a software system for implementing synthesized digital designs using VHDL so that the designs can be accepted by existing CAD systems to achieve low-level verification such as delay analysis and logic simulation as well as layout realization in various technologies.

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来源期刊

1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings

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